1. Field of the Invention
The present invention relates to a digital processor such as a microprocessor, a digital signal processor (DSP) or the like, and more particularly to a digital processor controlled by a microprogram.
2. Description of the Related Art
Digital processors having a plurality of processing circuits, a plurality of memory blocks, and a plurality of data buses for improved performance have recently been proposed and put to use. Such a digital processor comprises a data processing unit for carrying out arithmetic and logic operations and an instruction unit for controlling operation of processing circuits of the data processing unit, the data processing unit and the instruction unit being functionally separate from each other. The digital processor is described in detail in "COMPUTER ARCHITECTURE--A QUANTITATIVE APPROACH" written by David A. Patterson and John L. Hennessy, published by Morgan Kauhmann Publishers, Inc., page 208 (1990), for example.
FIG. 1A of the accompanying drawings shows an arrangement of a digital processing unit with a data processing unit having a plurality of internal data buses and a plurality of processing circuits. The digital processor has an instruction unit 51a for outputting a group of control signals S54 and a data processing unit 52 for carrying out the data processing operations in accordance with the control signals S54. The control signals S54 include control signals S54A, S54B, S54C (described later on).
The data processing unit 52 will first be described in detail. The data processing unit 52 comprises two data buses BUS0, BUS1 and two processing circuits including an arithmetic/logic unit (ALU) 52a and a multiplier 52b. The arithmetic/logic unit 52a and the multiplier 52b are controlled by the control signals S54A, S54B, respectively. Each of control signals S54A, S54B has a length of 5 bits. Each of the arithmetic/logic unit 52a and the multiplier 52b is connected to the data buses BUS0, BUS1, so that data D0, D1 on the data buses BUS0, BUS1 are supplied to both the arithmetic/logic unit 52a and the multiplier 52b. The arithmetic/logic unit 52a and the multiplier 52b can usually effectively operate exclusively of each other.
The instruction unit 51a has an instruction memory 53a and an instruction decoder 54a. The instruction memory 53a stores a plurality of instruction words for controlling operation of the data processing unit 52 and branching in an execution sequence. Depending on the operation to be carried out by the digital processor, a certain instruction word selected from the stored instruction words is supplied from the instruction memory 53a as an instruction signal S53a to the instruction decoder 54a.
The structure of instruction words will be described below with reference to FIG. 1B. The instruction signal S53a, i.e., each instruction word, has a length of 13 bits. The instruction word comprises two control fields A, B each having a length of 5 bits and a control field C having a length of 3 bits. The data represented by the control field A corresponds to the control signal S54A supplied to the ALU 52a, the data represented by the control field B to the control signal S54B supplied to the multiplier 52b, and the data represented by the control field C to the control signal S54C having a length of 3 bits which is used to control branching in an execution sequence. The instruction word is divided into the control signals S54A, S54B, S54C by the instruction decoder 54a. The control signal S54A is supplied to the ALU 52a, the control signal S54B to the multiplier 52b, and the control signal S54C to a circuit (not shown) for branching control.
As described above, either one of the ALU 52a and the multiplier 52b usually effectively operates exclusively of each other. Therefore, either one of the control fields A, B of each instruction word is not used for the storage of data. Such a condition is indicated by control fields that are represented by "-" in instruction words 59 stored in the instruction memory 53a as shown in FIG. 1A.
The conventional digital processor described above has problems in that the instruction memory for storing instruction words requires a large storage capacity to meet multifunction requirements and hence the large storage capacity of the instruction memory results in an increase in the cost of the digital processor.